Universal Verification Methodology

The Universal Verification Methodology (UVM) is a standardized methodology for verifying integrated circuit designs, with a planned release in early 2011.

In December 2009, a technical subcommittee of Accellera — a standards organization in the electronic design automation (EDA) industry — voted to establish the UVM and decided to base this new standard on the Open Verification Methodology (OVM-2.1.1)[1], a verification methodology developed jointly in 2007 by two EDA companies, Cadence Design Systems and Mentor Graphics.

On February 21, 2011, Accellera approved the 1.0 version of UVM[2]. UVM 1.0 includes a Reference Guide, a Reference Implementation in the form of a SystemVerilog base class library, and a User Guide.[3]. Aldec, Cadence, Mentor, and Synopsys support the 1.0 release of UVM.

References

1 ^ Accellera Status
2 ^ http://www.accellera.org/activities/vip
3 ^ Download from Accellera